/**
 @file sys_at_mac.h

 @author  Copyright (C) 2021 Centec Networks Inc.  All rights reserved.

 @date 2021-03-10

 @version v2.0

*/

#ifndef _SYS_AT_MAC_H
#define _SYS_AT_MAC_H
#ifdef __cplusplus
extern "C" {
#endif

/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
//#include "sys_usw_mac.h"

/****************************************************************
*
* Defines and Macros
*
****************************************************************/
enum sys_at_mac_fec_type_e
{
    SYS_AT_MAC_FEC_TYPE_NONE,          /**< [Arctic] FEC OFF */
    SYS_AT_MAC_FEC_TYPE_RS528,         /**< [Arctic] RS(528,514) */
    SYS_AT_MAC_FEC_TYPE_RS544,         /**< [Arctic] RS(544,514) */
    SYS_AT_MAC_FEC_TYPE_RS272,         /**< [Arctic] RS(272,257) */
    SYS_AT_MAC_FEC_TYPE_FC2112,        /**< [Arctic] FC(2112,2080) */
    SYS_AT_MAC_FEC_TYPE_RS544INT,      /**< [Arctic] RS(544,514)-Int, only for 100GR1 */
    SYS_AT_MAC_FEC_TYPE_RS272INT,      /**< [Arctic] RS(272,257)-Int, only for 100GR1 */
    SYS_AT_MAC_FEC_TYPE_MAX
};
typedef enum sys_at_mac_fec_type_e sys_at_mac_fec_type_t;

#define SYS_AT_MAC_CALENDAR_MULTI_FACTOR         1000
#define SYS_AT_MAC_CALENDAR_BUS_WIDTH_EPE        192
#define SYS_AT_MAC_CALENDAR_BUS_WIDTH_TX         96

#define SYS_AT_GET_PCSL_NUM_BY_MODE(mode, pcsl_num) do {\
        switch(mode)                                        \
        {                                                   \
            case CTC_CHIP_SERDES_XLG_MODE:                  \
            case CTC_CHIP_SERDES_LG_MODE:                   \
            case CTC_CHIP_SERDES_LG_R1_MODE:                \
            case CTC_CHIP_SERDES_XLG_R1_MODE:               \
            case CTC_CHIP_SERDES_XLG_R2_MODE:               \
                pcsl_num = 2;                               \
                break;                                      \
            case CTC_CHIP_SERDES_CG_MODE:                   \
            case CTC_CHIP_SERDES_CG_R2_MODE:                \
            case CTC_CHIP_SERDES_CG_R1_MODE:                \
                pcsl_num = 4;                               \
                break;                                      \
            case CTC_CHIP_SERDES_CCG_R4_MODE:               \
            case CTC_CHIP_SERDES_CCG_R2_MODE:               \
                pcsl_num = 8;                               \
                break;                                      \
            case CTC_CHIP_SERDES_CDG_R8_MODE:               \
            case CTC_CHIP_SERDES_CDG_R4_MODE:               \
                pcsl_num = 16;                              \
                break;                                      \
            case CTC_CHIP_SERDES_DCCCG_R8_MODE:             \
                pcsl_num = 32;                              \
                break;                                      \
            case CTC_CHIP_SERDES_XFI_MODE:                  \
            case CTC_CHIP_SERDES_XXVG_MODE:                 \
            default:                                        \
                pcsl_num = 1;                               \
                break;                                      \
        }                                                   \
    }while(0)

enum sys_at_mode_with_fec_speed_e
{
    AT_XFI_NONE,
    AT_XFI_FC2112,
    AT_XXVG_NONE,
    AT_XXVG_FC2112,
    AT_XXVG_RS528,
    AT_XLG_NONE,
    AT_XLG_FC2112,
    AT_LG_R2_NONE,
    AT_LG_R2_RS528,
    AT_LG_R2_RS544,
    AT_LG_R1_NONE,
    AT_LG_R1_RS528,
    AT_LG_R1_RS544,
    AT_LG_R1_RS272,
    AT_CG_R4_NONE,
    AT_CG_R4_RS528,
    AT_CG_R4_RS544,
    AT_CG_R2_NONE,
    AT_CG_R2_RS528,
    AT_CG_R2_RS544,
    AT_CG_R2_RS272,
    AT_CG_R1_RS544,
    AT_CG_R1_RS272,
    AT_CG_R1_RS544INT,
    AT_CG_R1_RS272INT,
    AT_CCG_R4_RS544,
    AT_CCG_R4_RS272,
    AT_CCG_R2_RS544,
    AT_CCG_R2_RS272,
    AT_CDG_R8_RS544,
    AT_CDG_R8_RS272,
    AT_CDG_R4_RS544,
    AT_CDG_R4_RS272,
    AT_DCCCG_R8_RS544,
    AT_DCCCG_R8_RS272,
    AT_NONE,
    AT_MAX_MODE_FEC
};
typedef enum sys_at_mode_with_fec_speed_e sys_at_mode_with_fec_speed_t;

struct sys_at_drv_ioctl_info_s
{
    uint32 tbl_id;
    uint32 fld_id;
    uint32 value;
    void*  ptr;
};
typedef struct sys_at_drv_ioctl_info_s sys_at_drv_ioctl_info_t;


enum sys_at_mcmac_pcs_cfg_e
{
    McMacPcsCfg_cfgAlternateEncode,
    McMacPcsCfg_cfgMcMacPcsSyncStatusDisable,
    McMacPcsCfg_cfgPcsTestMode,
    McMacPcsCfg_TOTAL_CNT
};
typedef enum sys_at_mcmac_pcs_cfg_e sys_at_mcmac_pcs_cfg_t;

enum sys_at_mcmac_mii_tx_config_list_item_e
{
    McMacMiiTx_cfgMcMacMiiTxBuffThrd,
    McMacMiiTx_cfgMcMacTxChanSpeed,
    McMacMiiTx_cfgMcMacTxLaneSpeed,
    McMacMiiTx_cfgMcMacTxRsFecEn,
    McMacMiiTx_cfgMcMacTxRsFecMode,
    McMacMiiTx_cfgMcMacTxAmInsertEn,
    McMacMiiTx_cfgMcMacTxAmInterval,
    McMacMiiTx_cfgMcMacMiiTxRdMask,
    McMacMiiTx_cfgMcMacMiiTxBuffLowThrd,
    McMacMiiTx_cfgMcMacTxOverClockEn,
    McMacMiiTx_TOTAL_CNT
};
typedef enum sys_at_mcmac_mii_tx_config_list_item_e sys_at_mcmac_mii_tx_config_list_item_t;

enum sys_at_mcmac_mii_rx_config_list_item_e
{
    McMacMiiRx_cfgMcMacMiiRxBuffMaxDepth,
    McMacMiiRx_cfgMcMacMiiRxLinkFilterEn,
    McMacMiiRx_cfgMcMacMiiRxFaultMaskLinkEn,
    McMacMiiRx_cfgMcMacMiiRxFaultFilterEn,
    McMacMiiRx_TOTAL_CNT
};
typedef enum sys_at_mcmac_mii_rx_config_list_item_e sys_at_mcmac_mii_rx_config_list_item_t;

enum sys_at_mcmac_pause_tx_ctl_list_item_e
{
    McMacPauseTxCtl_cfgMcMacTxPauseTimerDecValue,
    McMacPauseTxCtl_TOTAL_CNT
};
typedef enum sys_at_mcmac_pause_tx_ctl_list_item_e sys_at_mcmac_pause_tx_ctl_list_item_t;


enum sys_at_mcmac_credit_ctl_list_item_e
{
    McMacCreditCtl_cfgTxCreditThrd,
    McMacCreditCtl_TOTAL_CNT
};
typedef enum sys_at_mcmac_credit_ctl_list_item_e sys_at_mcmac_credit_ctl_list_item_t;

enum sys_at_mcmac_cal_ctrl_list_item_e
{
    McMacCalCtrl_cfgTxWalkerEnd,
    McMacCalCtrl_cfgRxWalkerEnd,
    McMacCalCtrl_cfgMcMacTxReady,
    McMacCalCtrl_cfgMcMacRxReady,
    McMacCalCtrl_TOTAL_CNT
};
typedef enum sys_at_mcmac_cal_ctrl_list_item_e sys_at_mcmac_cal_ctrl_list_item_t;

enum sys_at_mcmac_mac_tx_cfg_list_item_e
{
    McMacMacTx_cfgMcMacTxSendEn,
    McMacMacTx_cfgMcMacTxPktEn,
    McMacMacTx_cfgMcMacPmInterval,
    McMacMacTx_TOTAL_CNT
};
typedef enum sys_at_mcmac_mac_tx_cfg_list_item_e sys_at_mcmac_mac_tx_cfg_list_item_t;


enum sys_at_mcmac_mac_rx_cfg_list_item_e
{
    McMacMacRx_cfgMcMacRxSpeed,
    McMacMacRx_cfgMcMacRxPktEn,
    McMacMacRx_TOTAL_CNT
};
typedef enum sys_at_mcmac_mac_rx_cfg_list_item_e sys_at_mcmac_mac_rx_cfg_list_item_t;

enum sys_at_mcmac_reset_list_e
{
    McMac_MacRxSoftReset,
    McMac_MiiRxSoftReset,
    McMac_MacTxSoftReset,
    McMac_MiiTxSoftReset
};
typedef enum sys_at_mcmac_reset_list_e sys_at_mcmac_reset_list_t;

enum sys_at_mcpcs_800_en_clk_list_e
{
    McPcs800EnClk_enClkMcFecCore0,
    McPcs800EnClk_enClkMcFecCore1,
    McPcs800EnClk_enClkMcPcs400Core0,
    McPcs800EnClk_enClkMcPcs400Core1,
    McPcs800EnClk_enClkMcPcs800
};
typedef enum sys_at_mcpcs_800_en_clk_list_e sys_at_mcpcs_800_en_clk_list_t;

enum sys_at_mcpcs_800_soft_reset_list_e
{
    McPcs800_cfgSoftResetMcFecRx0,
    McPcs800_cfgSoftResetMcFecRx1,
    McPcs800_cfgSoftResetMcFecTx0,
    McPcs800_cfgSoftResetMcFecTx1,
    McPcs800_cfgSoftResetMcFec0,
    McPcs800_cfgSoftResetMcFec1,
    McPcs800_cfgSoftResetMcPcs0,
    McPcs800_cfgSoftResetMcPcs1,
    McPcs800_cfgSoftResetMcPcsReg0,
    McPcs800_cfgSoftResetMcPcsReg1,
    McPcs800_cfgSoftResetRxChanBmp,
    McPcs800_cfgSoftResetTxChanBmp,
    McPcs800_TOTAL_CNT
};
typedef enum sys_at_mcpcs_800_soft_reset_list_e sys_at_mcpcs_800_soft_reset_list_t;

enum sys_at_mcpcs_800_phy_config_list_item_e
{
    McPcs800PhyLane_cfgPmaWidth,
    McPcs800PhyLane_cfgLaneBitDemuxEn,
    McPcs800PhyLane_cfgFcFecEn,
    McPcs800PhyLane_cfgRsFecEn,
    McPcs800PhyLane_cfgTxLaneAsyncFifoAFullThrd,
    McPcs800PhyLane_cfgTxLaneAsyncFifoStartThrd,
    McPcs800PhyLane_cfgTxBufStartRdThrd,
    McPcs800PhyLane_cfgTxAsyncFifoCreditThrd,
    McPcs800PhyLane_TOTAL_CNT,
    McPcs800PhyLane_cfgTxChanId,
    McPcs800PhyLane_cfgTxLaneId,
    McPcs800PhyLane_cfgRxChanId,
    McPcs800PhyLane_cfgRxLogicLaneId
};
typedef enum sys_at_mcpcs_800_phy_config_list_item_e sys_at_mcpcs_800_phy_config_list_item_t;

enum sys_at_mcpcs_400_rx_lane_config_list_item_e
{
    McPcs400RxLane_cfgRxChanSpeed,
    McPcs400RxLane_cfgRxLaneSpeed,
    McPcs400RxLane_cfgRxAmInterval,
    McPcs400RxLane_cfgRxRsFecEn,
    McPcs400RxLane_cfgRxCwmLockFsmMode,
    McPcs400RxLane_cfgRxCl161Mode,
    McPcs400RxLane_TOTAL_CNT
};
typedef enum sys_at_mcpcs_400_rx_lane_config_list_item_e sys_at_mcpcs_400_rx_lane_config_list_item_t;

enum sys_at_mcpcs_400_rx_config_list_item_e
{
    McPcs400Rx_cfgRxFecMode,
    McPcs400Rx_cfgRxDskMaxAddr,
    McPcs400Rx_cfgRxFecCwmSfBitsEn,
    McPcs400Rx_TOTAL_CNT
};
typedef enum sys_at_mcpcs_400_rx_config_list_item_e sys_at_mcpcs_400_rx_config_list_item_t;

enum sys_at_mcpcs_400_tx_chan_cfg_list_item_e
{
    McPcs400TxChanCfg_cfgTxCodecSelChan,
    McPcs400TxChanCfg_cfg100GCwmMode,
    McPcs400TxChanCfg_cfgTxFecChan,
    McPcs400TxChanCfg_cfgCl161Mode,
    McPcs400TxChanCfg_TOTAL_CNT
};
typedef enum sys_at_mcpcs_400_tx_chan_cfg_list_item_e sys_at_mcpcs_400_tx_chan_cfg_list_item_t;

enum sys_at_mcpcs_400_rx_fec_chan_map_list_item_e
{
    McPcs400RxFecChanMap_cfgFec0Chan_PcsChan,
    McPcs400RxFecChanMap_cfgFec1Chan_PcsChan,
    McPcs400RxFecChanMap_cfgPcsChan_CodecSel,
    McPcs400RxFecChanMap_cfgPcsChan_FecChan,
    McPcs400RxFecChanMap_TOTAL_CNT
};
typedef enum sys_at_mcpcs_400_rx_fec_chan_map_list_item_e sys_at_mcpcs_400_rx_fec_chan_map_list_item_t;

enum sys_at_mcpcs_400_pma_cfg_list_item_e
{
    McPcs400PmaCfg_cfgRxAutoRecoverEnLane,
    McPcs400PmaCfg_cfgTxAsyncFifoUnderrunEnLane,
    McPcs400PmaCfg_cfgTxLaneRstPatLane,
    McPcs400PmaCfg_cfgTxPatModeLane,
    McPcs400PmaCfg_TOTAL_CNT
};
typedef enum sys_at_mcpcs_400_pma_cfg_list_item_e sys_at_mcpcs_400_pma_cfg_list_item_t;

enum sys_at_hss_lane_cfg_list_item_e
{
    HssLaneCfg_cfgAnethTxReadyLane,
    HssLaneCfg_cfgForcePmaReady4AnethEnLane,
    HssLaneCfg_cfgForcePmaReady4AnethValueLane,
    HssLaneCfg_cfgForcePmaReady4PcsEnLane,
    HssLaneCfg_cfgForcePmaReady4PcsValueLane,
    HssLaneCfg_cfgForcePmaReady4SyncEEnLane,
    HssLaneCfg_cfgForcePmaReady4SyncEValueLane,
    HssLaneCfg_cfgHssTxOutSelLane,
    HssLaneCfg_cfgPmaReady4AnethMaskLane,
    HssLaneCfg_cfgPmaReady4PcsMaskLane,
    HssLaneCfg_cfgPmaReady4SyncEMaskLane,
    HssLaneCfg_TOTAL_CNT
};
typedef enum sys_at_hss_lane_cfg_list_item_e sys_at_hss_lane_cfg_list_item_t;

enum sys_at_mcpcs_400_mcfec_cfg_list_item_e
{
    McPcs400McFecCfg_cfg2ln1En,
    McPcs400McFecCfg_TOTAL_CNT
};
typedef enum sys_at_mcpcs_400_mcfec_cfg_list_item_e sys_at_mcpcs_400_mcfec_cfg_list_item_t;

enum sys_at_mchata_soft_reset_cfg_list_item_e
{
    McHataSoftResetCfg_RxSoftReset,
    McHataSoftResetCfg_TxSoftReset,
    McHataSoftResetCfg_TOTAL_CNT
};
typedef enum sys_at_mchata_soft_reset_cfg_list_item_e sys_at_mchata_soft_reset_cfg_list_item_t;

enum sys_at_mchata_enable_list_item_e
{
    McHataEnable_RxEnable,
    McHataEnable_TxEnable,
    McHataEnable_TOTAL_CNT
};
typedef enum sys_at_mchata_enable_list_item_e sys_at_mchata_enable_list_item_t;

enum sys_at_mchata_rx_cfg_list_item_e
{
    McHataRsCfg_Mode,
    McHataRsCfg_TOTAL_CNT
};
typedef enum sys_at_mchata_rx_cfg_list_item_e sys_at_mchata_rx_cfg_list_item_t;

enum sys_at_mchata_tx_chan_map_list_item_e
{
    McHataTxChanMap_ChanMap,
    McHataTxChanMap_TOTAL_CNT
};
typedef enum sys_at_mchata_tx_chan_map_list_item_e sys_at_mchata_tx_chan_map_list_item_t;

/*pause ability bit value*/
enum sys_at_asmdir_pause_value_e
{
    SYS_AT_ASMDIR_0_PAUSE_0        = 0,  //ASM_DIR 0, PAUSE 0
    SYS_AT_ASMDIR_0_PAUSE_1        = 1,  //ASM_DIR 0, PAUSE 1
    SYS_AT_ASMDIR_1_PAUSE_0        = 2,  //ASM_DIR 1, PAUSE 0
    SYS_AT_ASMDIR_1_PAUSE_1        = 3,  //ASM_DIR 1, PAUSE 1
    SYS_AT_ASMDIR_PAUSE_BUTT
};
typedef enum sys_at_asmdir_pause_value_e sys_at_asmdir_pause_value_t;


/*
enum sys_at_mcpcs_table_e
{
    McPcs_Table_800EnClk;
    McPcs_Table_800Reset;
    McPcs_Table_800TxPhyLaneCfg;
    McPcs_Table_800RxPhyLaneCfg;
    McPcs_Table_400RxLaneCfg;
    McPcs_Table_400RxChanCfg;
    McPcs_Table_400TxChanCfg;
    MCPcs_Table_TOTAL_CNT
};
typedef enum sys_at_mcpcs_table_e sys_at_mcpcs_table_t;

enum sys_at_mcmac_table_e
{
    McMac_Table_RxSoftReset;
    McMac_Table_RxCfg;
    McMac_Table_TxSoftReset;
    McMac_Table_MacTxCfg;
    McMac_Table_MiiTxCfg;
    McMac_Table_TxChanIdLaneCfg;
    McMac_Table_CreditCtl;
    McMac_Table_CalCtrl;
    McMac_Table_TxCal;
    McMac_Table_StatsInit;
    McMac_Table_TOTAL_CNT
};
typedef enum sys_at_mcmac_table_e sys_at_mcmac_table_t;


enum sys_at_mchata_table_e
{
    McHata_Table_RxSoftReset;
    McHata_Table_RxEnable;
    McHata_Table_TxSoftReset;
    McHata_Table_TxEnable;
    McHata_Table_RsFecMode; 
    McHata_Table_TxChanMap;
    McHata_Table_TOTAL_CNT
};
typedef enum sys_at_mchata_table_e sys_at_mchata_table_t;

enum sys_at_hw_table_module_e
{
    Hw_Module_McMac,
    Hw_Module_McPcs,
    Hw_Module_McHata,
    Hw_Module_TOTAL_CNT
};
typedef enum sys_at_hw_table_module_e sys_at_hw_table_module_t;

struct sys_at_hw_table_info_s
{
    uint8  module_type;
    uint32 field_base;
    uint8  field_step;
    uint32 field_offset;
    uint8  is_bmp;
    uint8  value;
    uint8  bmp_offset;
};
typedef struct sys_at_hw_table_info_s sys_at_hw_table_info_t; */



#ifdef __cplusplus
}
#endif

#endif
